EEPROM

EEPROM

Electrically Erasable Programmable Read-Only Memory (EEPROMEEPROMHardwareNon-volatile card memory for data.Click to view →) is the primary non-volatile storage technology used in smart card chips for persisting data that must survive power cycles — including cryptographic keys, certificates, PIN counters, application data, and file system structures. Unlike ROM, which is fixed during chip fabrication, EEPROM can be written and erased electrically during the card's operational lifetime.

EEPROM in Smart Card Architecture

A typical smart card chip partitions its memory across three types:

EEPROM stores everything that must persist between card sessions: the JavaCard applet code, GlobalPlatform security domain keys, cardholder data written during electrical personalization, and runtime counters such as PIN retry counts and transaction logs.

Write Characteristics

EEPROM writing is significantly slower than reading and consumes more power:

• Write time: 3-10 ms per page (32-128 bytes), compared to microseconds for reads
• Endurance: 100,000 to 500,000 write/erase cycles per cell before wear-out
• Write granularity: Page-level (cannot write individual bytes on most smart card EEPROMs)
• Power requirement: Internal charge pump generates the high voltage (10-15V) needed for Fowler-Nordheim tunneling

The limited write endurance is a practical design constraint. Applications must minimize unnecessary writes — for instance, buffering transaction counters in RAM and committing to EEPROM only at session close.

EEPROM vs Flash Memory

Modern high-capacity smart cards are increasingly migrating to Flash memory, which offers higher density, faster write speeds, and lower power consumption. However, EEPROM retains advantages for smart card use cases:

Security Considerations

EEPROM contents are a prime target for physical attacks. Micro-probing with focused ion beam (FIB) equipment can read memory cells directly. To counter this, Secure Element chips encrypt EEPROM contents with an on-chip key, scramble the physical memory layout, and implement active shield meshes that detect probing attempts and trigger data zeroization.